1. Technical Field
The present invention relates to computer data systems, more particularly to memory controllers, and still more particularly to an improved method and system for reducing memory power consumption while increasing memory performance.
2. Description of the Related Art
Memory banks in computer systems consume a significant portion of a computer system's power. Although memory components usually support multiple power reduction modes (e.g., Self Refresh and Power Down in SDRAM), such support is typically not utilized in systems. Simple power reduction techniques that power down memory banks after completing a request are not attractive because of the performance penalty associated with waking up the memory at the next request.
Therefore, there is a need for a system and method to allow the utilization of power reduction techniques for memory while reducing the associated performance penalty.